Universal Verification Methodology (UVM) + Project Demo

This course covers the topics, basics of UVM methodology, components, Objects, UVM Factory, configuration, phases, Reports. Step wise approach to build testbench using driver, sequencer, agent, environment, test and top test bench. Building sequences for verifying the features of an example IP. Outcome of this course, one can develop UVM testbench and testcases right from the scratch. The course is also covering an example test bench creation and explains how to write testcases. How to simulate. This is demonstrated with one simulator. This course is useful for Students, who are studying BE/BTech/MTech in Electronics and communication and want to learn UVM, do internship. Also those who have completed Engineering , can opt for this course and learn UVM, simulate with free tools available in edaplayground. This is a complete course with project demonstration and contains the assignments to make the UVM learning easy. The agenda is as follows: Session 01 – UVM OverviewSession 02 – UVM Components and ObjectsSession 03 – TLM Session 04 – UVM FactorySession 05 – UVM ConfigurationSession 06 – UVM PhasesSession 07-1 – UVM ReportSession 07-2 – UVM Report ExampleSession 08 – UVM Sequencer, DriverSession 09 – UVM Agent, MonitorSession 10 – UVM Test, ScoreboardSession 11 – UVM TopologySession 12-1 – Test sequences part 1Session 12-2 – Test sequences part 2AssignmentsOnce you go through the course, you can apply and get job in semiconductor companies as design verification engineer.