Synthesizable VHDL Programming and FPGAs
In this course, we will teach VHDL programming. The fundamental concepts about VHDL programming will be provided. In addition, practical examples using FPGA development boards will be provided. Combinational and clocked logic circuit design will be explained by examples. We will use either ISR or VIVADO platform for the simulation and development of VHDL programs. Some of the written programs will be loaded into FPGA cards for demonstration purposes.
Introduction
Course outline is briefly explained
Entity, Architecture and VHDL Operators
ENTITY module in VHDL is explained by example.
Architecture unit in VHDL is explained by examples.
Data objects, such as signal, constant, variable are explained by examples.
Data types are explained by examples.
VHDL Operators such as ·assignment Operators, logical Operators, logical and arithmetic shift operators are explained.
VHDL Operators, rem, mod, rem, abs, &, ** are explained by examples
The use of 'generic' statement in VHDL is explained by examples.
Combinational Circuit Design in VHDL
Combinational circuit design using "when" and "with-select" statements is explained by examples.
The VHDL Statement "Generate" is explained by examples
Implementation of MUXES and circuits involving MUXES in VHDL is explained by examples.
VHDL implementation of logic circuits involving MUXES is explained by examples.
VHDL implementation of logic circuits involving MUXES is explained by examples.
Gray, BCD, Octal, and binary Prority Encoders are implemented in VHDL
In this lecture BCD encoder and BCD to Sevent Segment Display Code Converter will be implemented in VHDL
Simulation of VHDL Programs, and Testbench Writing
In this lecture the students will learn how to write a testbench for the simulation of VHDL programs.
Testbench writing will be exaplained by an example
User Defined Data Types, Constrained and Unconstrained Arrays, Matrices in VHDL
In this lecture, user defined data types involving enumerated data types and constrained arrays are explained by examples.
In this lecture, unconstrained array definitions and use of the port arrays are explained by examples
In this lecture the definitions of matrices , 3D arrays and higher dimensional matrices and their use will be explained. How to access to the elements of arrays or matrices are explained by examples.
Sequential circuits, process, clock divider, sample seq. circ. implementations
In this lecture, the students will learn the implementation of sequential circuits in VHDL. Process, if-then-else statement, and D-flip flop implementation are explained.
In this lecture, JK Flip-Flop, T Flip-Flop, Counter and MUX implementation in VHDL using Process are explained.
In this lecture, operations of digital circuits used for clock division operation are explained
In this lecture, implementation of clock divider or frequency divider in VHDL language is explained and various VHDL clock divider examples are provided.
In this lecture, we write the necessary VHDL codes to drive a seven segment display that shows the digits from 0 to 9 for one second duration each.
VHDL Statements, Wait, Wait On, Wait Until and Wait For
The VHDL statements WAIT, WAIT ON, WAIT UNTIL and WAIT FOR are explained by examples
Programming FPGA Using ARTY-7 35T Evaluation Board and VIvado
In this lecture, the students will learn how to program FPGA using ARTY-7 35T Evaluation Board and XILINX VIVADO
