Synthesizable VHDL Programming and FPGAs
- Description
- Curriculum
- FAQ
- Reviews
In this course, we will teach VHDL programming. The fundamental concepts about VHDL programming will be provided. In addition, practical examples using FPGA development boards will be provided. Combinational and clocked logic circuit design will be explained by examples. We will use either ISR or VIVADO platform for the simulation and development of VHDL programs. Some of the written programs will be loaded into FPGA cards for demonstration purposes.
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ENTITY in VHDLENTITY module in VHDL is explained by example.
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ARCHITECTURE in VHDL
Architecture unit in VHDL is explained by examples.
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Data Objects in VHDL
Data objects, such as signal, constant, variable are explained by examples.
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Data types
Data types are explained by examples.
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VHDL Operators, assignment operators, logical ops, logical and arithmetic ops
VHDL Operators such as ·assignment Operators, logical Operators, logical and arithmetic shift operators are explained.
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VHDL Operators, rem, mod, rem, abs, &, **
VHDL Operators, rem, mod, rem, abs, &, ** are explained by examples
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Generic Statement
The use of 'generic' statement in VHDL is explained by examples.
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When and With-Select Statements
Combinational circuit design using "when" and "with-select" statements is explained by examples.
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VHDL Generate Statement
The VHDL Statement "Generate" is explained by examples
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MUXES in VHDL, Part-1
Implementation of MUXES and circuits involving MUXES in VHDL is explained by examples.
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MUXES in VHDL, Part-2
VHDL implementation of logic circuits involving MUXES is explained by examples.
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MUXES in VHDL, Part-3
VHDL implementation of logic circuits involving MUXES is explained by examples.
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Binary Encoders in VHDL
Gray, BCD, Octal, and binary Prority Encoders are implemented in VHDL
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BCD Encoder and BCD to SS Display Converter in VHDL
In this lecture BCD encoder and BCD to Sevent Segment Display Code Converter will be implemented in VHDL
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User defined data types and contrained arrays in VHDL
In this lecture, user defined data types involving enumerated data types and constrained arrays are explained by examples.
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Unconstrained arrays and port arrays
In this lecture, unconstrained array definitions and use of the port arrays are explained by examples
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Matrices and 3D arrays in VHDL
In this lecture the definitions of matrices , 3D arrays and higher dimensional matrices and their use will be explained. How to access to the elements of arrays or matrices are explained by examples.
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Process, if-then-else, D-flip flop in VHDL are explained
In this lecture, the students will learn the implementation of sequential circuits in VHDL. Process, if-then-else statement, and D-flip flop implementation are explained.
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JK Flip-Flop, T Flip-Flop, Counter and MUX implementation in VHDL using Process
In this lecture, JK Flip-Flop, T Flip-Flop, Counter and MUX implementation in VHDL using Process are explained.
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Clock divider digital circuits
In this lecture, operations of digital circuits used for clock division operation are explained
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Clock divider (frequency divider) implementation in VHDL
In this lecture, implementation of clock divider or frequency divider in VHDL language is explained and various VHDL clock divider examples are provided.
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SS Display Driver Implementation in VHDL
In this lecture, we write the necessary VHDL codes to drive a seven segment display that shows the digits from 0 to 9 for one second duration each.
