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3.85
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Synthesizable VHDL Programming and FPGAs

Circuit Design Using VHDL for FPGA Devices
Synthesizable VHDL Circuit Design and FPGA programming using VHDL

In this course, we will teach VHDL programming. The fundamental concepts about VHDL programming will be provided. In addition, practical examples using FPGA development boards will be provided. Combinational and clocked logic circuit design will be explained by examples. We will use either ISR or VIVADO platform for the simulation and development of VHDL programs. Some of the written programs will be loaded into FPGA cards for demonstration purposes.

Introduction

1
Outline

Course outline is briefly explained

Entity, Architecture and VHDL Operators

1
ENTITY in VHDL

ENTITY module in VHDL is explained by example.

2
ARCHITECTURE in VHDL

Architecture unit in VHDL is explained by examples.

3
Data Objects in VHDL

Data objects, such as signal, constant, variable are explained by examples.

4
Data types

Data types are explained by examples.

5
VHDL Operators, assignment operators, logical ops, logical and arithmetic ops

VHDL Operators such as ·assignment Operators, logical Operators, logical and arithmetic shift operators are explained.

6
VHDL Operators, rem, mod, rem, abs, &, **

VHDL Operators, rem, mod, rem, abs, &, ** are explained by examples

7
Generic Statement

The use of 'generic' statement in VHDL is explained by examples.

Combinational Circuit Design in VHDL

1
When and With-Select Statements

Combinational circuit design using "when" and "with-select" statements is explained by examples.

2
VHDL Generate Statement

The VHDL Statement "Generate" is explained by examples

3
MUXES in VHDL, Part-1

Implementation of MUXES and circuits involving MUXES in VHDL is explained by examples.

4
MUXES in VHDL, Part-2

VHDL implementation of logic circuits involving MUXES is explained by examples.

5
MUXES in VHDL, Part-3

VHDL implementation of logic circuits involving MUXES is explained by examples.

6
Binary Encoders in VHDL

Gray, BCD, Octal, and binary Prority Encoders are implemented in VHDL

7
BCD Encoder and BCD to SS Display Converter in VHDL

In this lecture BCD encoder and BCD to Sevent Segment Display Code Converter will be implemented in VHDL

Simulation of VHDL Programs, and Testbench Writing

1
Testbench writing for the simulation of VHDL programs

In this lecture the students will learn how to write a testbench for the simulation of VHDL programs.

2
Example for testbench writing

Testbench writing will be exaplained by an example

User Defined Data Types, Constrained and Unconstrained Arrays, Matrices in VHDL

1
User defined data types and contrained arrays in VHDL

In this lecture, user defined data types involving enumerated data types and constrained arrays are explained by examples.

2
Unconstrained arrays and port arrays

In this lecture, unconstrained array definitions and use of the port arrays are explained by examples

3
Matrices and 3D arrays in VHDL

In this lecture the definitions of matrices , 3D arrays and higher dimensional matrices  and their use will be explained. How to access to the elements of arrays or matrices are explained by examples.

Sequential circuits, process, clock divider, sample seq. circ. implementations

1
Process, if-then-else, D-flip flop in VHDL are explained

In this lecture, the students will learn the implementation of sequential circuits in VHDL. Process, if-then-else statement, and D-flip flop implementation are explained.

2
JK Flip-Flop, T Flip-Flop, Counter and MUX implementation in VHDL using Process

In this lecture, JK Flip-Flop, T Flip-Flop, Counter and MUX implementation in VHDL using Process are explained.

3
Clock divider digital circuits

In this lecture, operations of digital circuits used for clock division operation are explained

4
Clock divider (frequency divider) implementation in VHDL

In this lecture, implementation of clock divider or frequency divider in VHDL language is explained and various VHDL clock divider examples are provided.

5
SS Display Driver Implementation in VHDL

In this lecture, we write the necessary VHDL codes to drive a seven segment display that shows the digits from 0 to 9 for one second duration each.

VHDL Statements, Wait, Wait On, Wait Until and Wait For

1
VHDL Statements, Wait, Wait On, Wait Until and Wait For

The VHDL statements WAIT, WAIT ON, WAIT UNTIL and WAIT FOR are explained by examples

Programming FPGA Using ARTY-7 35T Evaluation Board and VIvado

1
Programming FPGA Using ARTY-7 35T Evaluation Board and XILINX VIVADO

In this lecture, the students will learn how to program FPGA using  ARTY-7 35T Evaluation Board and XILINX VIVADO

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8 hours on-demand video
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Certificate of Completion
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