VIVADO Xilinx FPGA -Learn From The Beginning (+PCIe project)
- Description
- Curriculum
- FAQ
- Reviews
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In this course you will learn how to use VIVADO tool to develop Xilinx FPGAs.
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As it’s easy for you to understand, working as an FPGA developer is the most profitable job in the Hardware development industry. And by now, it is a profession with great demand in every big company: Apple, Microsoft, Intel, Amazon, Google and many others!
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If you want to work as an FPGA developer or just to know how to design an FPGA this is the course for you!
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This Course is in English and has subtitles to 16 different languages!
This Course was made for all levels by a professional electronic and computer engineer. with a huge experience with FPGAs of all of the companies in the market. In this Course we will learn how to use Xilinx FPGAs tool – Vivado design suite.
Students saying:
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Paul Burciu: “I appreciate the course as a good one, giving me valuable information about how to program an FPGA board using Vivado and providing such a complex application regarding FPGA implementation of PCI Express. I am thanking the author for his great work on this course.”
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Umesh kumar Sharma: “It’s very informative and helpful. I learn many things here. It’s great opportunity for us. I loved it.”
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Amos TangUpdated: “Ofer is a great and active coach.”
In this course you will learn everything you need to know for using Vivado design suite. Vivado design suite is a tool that was crated by Xilinx and is used to design Xilinx FPGAs, simulating them and real-time debugging them and of course to program them.
This course was created for beginners who never used Vivado before, and also for students who wants more experience with the Vivado design suite, also this course can help even advanced users for knowing and understanding how to use and design more complex parts in this tool – like Pcie, Axi interface, Simulations with 3rd party tool(Modelsim,Questasim…), Zynq7000 processor and much more.
This course will help the Students understand everything they needs to know for working in big companies with Vivado design suite as a professional designers.
In this course the students will learn how to simulate their project with Vivado and also with 3rd party tool – Modelsim. Students with no experience at Modelsim will learn briefly about Modelsim but i can guarantee that after the Full Project part in the course you will control the Modelsim which is a really easy tool to learn.
At the end of the course it includes a Full Project of 2.5 hours, with PCIE communication and simulating the PCIE Cores. This way after you have learned all of the parts of how to start your own project, you can also go and build a big project by using all of the aspects learned on this course.
The course will start with installing Vivado tool and Modelsim. The next of the course I will create a project and explain step by step, after that in the last 2 lectures I will create the second complex project of PCIe and explain everything.
We cover a wide variety of topics, including:
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How to download and install Vivado design suite 2019.1
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How to download and install Modelsim
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Create new project
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Adding block design
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Adding Xilinx IP cores
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Xilinx Primitive Cores
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Xilinx language templates
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synthesize a project
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Implementing the design
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Creating Constraints
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Generate Bitstream , Binstream and MCS files
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Simulating the design through Vivado or Modelsim
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Zynq 7000
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Axi interfaces
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Open SDK project
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Real Time Integration with ILA – logic analyser
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PCIE FULL Project with PCIE and Simulating the PCIE.
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and much more!
You will get lifetime access to over 30 lectures!
This course comes with a 30 day money back guarantee! If you are not satisfied in any way, you’ll get your money back.
So what are you waiting for? Learn FPGA Development in a way that will advance your career and increase your knowledge, all in a fun and practical way!
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1
Introduction and Overview of the course VIVADO Xilinx FPGA - Learn from the...In this lecture i will explain about the course content.
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2
Downloading and installing Vivado 2019.1 Xilinx FPGA tool
How to download and install Vivado 2019.1
Xilinx site might change during the time, i added links for the downloading section under Xilinx site.
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3
Downloading and installing ModelSim simulation tool
In this lecture you will learn how to download modelsim for students edition.
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4
How to open a new project in VIVADO Xilinx FPGA tool
This lecture will explain you how to use the vivado after starting new project. Walk you through the buttons and options of the vivado tool.
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5
How to open an existing project in VIVADO Xilinx FPGA tool
This lecture will explain you how to open existing project in vivado
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6
How to open an example project in VIVADO Xilinx FPGA tool
Xilinx added example projects so you can use them as a reference for your design, it will help you understand how to connect different IP cores together.
In this lecture will explain to you how to open Vivado example project.
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7
How to add files to a project in VIVADO Xilinx FPGA tool
This lecture will explain to you how to add existing files to the project
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8
Adding Block design to the project in VIVADO Xilinx FPGA tool
This lecture explain how to add a block design and connect it to out project
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9
IP Cores and Opening Xilinx IP Example Design in VIVADO Xilinx FPGA tool
This lecture will explain you what IP Cores are and how to open Xilinx IP example design
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10
Language templates- Primitive Cores in VIVADO Xilinx FPGA tool
This lecture will explain you what primitives are and how to add them to your design
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11
Run Synthesis in VIVADO Xilinx FPGA tool
In this lecture you will learn how to synthesize your design.
The synthesis running on the VHDL file in the vivado and check your logic for error and creating a full map of components(LUTS).
It is almost like compilation but for vhdl files in vivado tool.
The synthesis can also tell you how many LUTS u need for your project.
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12
Run Implementation in VIVADO Xilinx FPGA tool
In this lecture you will learn how to run Implementation and check the error and warnings logs.
The implementation is taking the project that you have created and fit it to the fpga that you choose.
This is like Place and route. So every fpga has different timing methods, this part of the tool will place the project as it should so the timing will be the best on your fpga.
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13
Creating Constraints file in VIVADO Xilinx FPGA tool
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14
Constraints Wizard in VIVADO Xilinx FPGA tool
In this lecture you will learn to create Constraints.
The constraints are set of orders that will be used for putting Vivado limits, but are not forcing the it.
When Vivado is running the implementation it will consider the constraints first but will not force itself to these limits.
If one of the limits can't be achieve, Vivado will warn you about it.
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15
Language templates in VIVADO Xilinx FPGA tool
In this lecture you will learn how to use language templates.
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16
View RTL schematic in VIVADO Xilinx FPGA tool
In this lecture you will learn how to see the RTL schematic.
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17
Creating a Bit file in VIVADO Xilinx FPGA tool
In this lecture you will learn how to create Bitstream file(.bit file).
The Bit file is used for programming the Fpga with your project. Note that the Bit file will be loaded through JTAG which is the programmer and after every shutdown of the FPGA that have been loaded with Bit file is deleted.
A Bit file is loading the FPGA with your project until you shutdown the power of the FPGA, If you want the FPGA to load with your project every time you need a FLASH memory and an MCS or Bin file(both of the created from the bit file so this lecture is a must to know) - in the next lecture.
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Load Bit file to the FPGA in VIVADO Xilinx FPGA tool
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19
Creating Bin file or Mcs file through the VIVADO for Ultrascale or 7 series
In this lecture you will learn how to generate a Bin and Mcs files from the Bit file Through the VIVADO, this method is right for Ultrascales and 7 series FPGAs.(for the ZYNQ process MCS file i am explaining at the SDK part at this course).
Mcs and Bin files are used for flash memory, so the FPGA can load itself after every shutdown from an outside flash memory.
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20
running vivado simulation in VIVADO Xilinx FPGA tool
The simulation tool helps designers check their VHDL code.
Even that inside FPGA we know we can have timing problems that cannot be solved with simulations, the simulator can give us a first clue of how to fix our problems and to fix our coding problems
In this lecture you will learn how to add your test bench file(simulation VHDL file) and how to run the Vivado simulator.
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21
Modelsim Configuration in VIVADO Xilinx FPGA tool
Modelsim is a third party tool for VHDL simulation, the strongest tool for simulation actually.
Using modelsim can make an easier life for the developer.
In this lecture you will learn how to configure Vivado so it will be able to run the Vivado project inside Modelsim simulator tool.
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22
Running and using Modelsim simulator
In this lecture you will learn how to run the Modelsim simulator from vivado.
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25
Export Hardware - Creating HDF file in VIVADO Xilinx FPGA tool
How to create hdf file for the zynq7000(the ps part on the fpga) which is the processing system.
We need the hdf file for the next lecture, and it will be used inside the sdk for loading the connection between the PL and the PS.
PL = programmable logic(fpga part) , PS = processing system(cpu inside the fpga)
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26
Open SDK New Project and create mcs/bin file in SDK Xilinx FPGA tool
How to open the SDK, the SDK is a tool for programming the cpu part (PS) inside the FPGA. Very similar to eclipse(for programmer)
We will learn how to open new project and how to use our previous lecture .hdf file from our project.
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27
Generate MCS or Bin file and load it to the QSPI - Zynq7000 in SDK Xilinx FPGA
In this lecture you will learn how to create MCS or Bin file for the ZYNQ7000 and how to load it, and i will show you how to run the hello world on a development board.
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28
Creating ILA in VIVADO Xilinx FPGA tool
In this lecture you will learn how to create ILA - integrated logic analyzer. The ILA is like Signal-Tap of Altera's FPGAs.
The ILA is good for checking your FPGA in real-time. The ILA is an inside core that can be connected in parallel to any place inside
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29
Creating Bit File with .ltx files and Run the ILA for real-time debug in VIVADO
In this lecture i will teach you how to run the ILA on the FPGA and debug your project in Real-Time!
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30
Creating the PCIe full project in VIVADO Xilinx FPGA tool
In this lecture you will learn how to create a full project with PCIE from the start to the end.
This lecture includes a second part on the next lecture for simulating this project.
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31
Simulating the PCIe full project in Modelsim
In this lecture you will learn how to simulate the full project.
