SystemVerilog Interface - get, set, go!

About SystemVerilog (SV):

SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for verification, design and synthesis. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of a complete Object-Oriented paradigm features. There are also considerable improvements in the usability of Verilog for RTL design.

What’s SV Interface?

One of the key features of SystemVerilog is interfaces – a key element that is common to both RTL designers and verification engineers. In this course, you will learn the motivation to use interfaces, get deep into the syntax and semantics of the construct. The course also includes a set of industry examples to show how this is used in real life.

Objectives:

We will leverage on one of our webinars delivered along with our technology partner. Main objectives of this short course are:

• Introduce SystemVerilog interface

• Provide detailed syntax on SV Interface

• Show interface as wire-bundle and how it is beneficial to users

• Show how SV interfaces are much more than just “wire bundle” – via assertions, coverage etc.

• We will also add  Quiz at the end

Prerequisites:

Attendees must be familiar with Verilog and ideally, but not essentially, Verilog2001. No prior knowledge of SystemVerilog is required. If you have queries on these prerequisites, please contact CVC.

We will cover the following:

1.Introduction to CVC

2. SystemVerilog interface introduction

3. Verilog ports vs. SystemVerilog interfaces

4. Syntax details of SystemVerilog interface construct

5. Using Assertions inside SystemVerilog interfaces

6. Case studies on successful SV interface usage

7. We will wrap up with a quiz