Designing Digital Systems Using VHDL - An introduction
- Description
- Curriculum
- FAQ
- Reviews
Description
In RAHDG 432 we’ll Focus on designing different types of digital systems using VHDL language code then we simulate those in the ISE software and at the end we do the implementation. It includes Design and analysis of latches and flip-flops. Number of digital designs have been designed in VHDL language to make you understand them better.
This course describes the different types of design units in VHDL such as entity, architecture, configuration, package and package body. The design and analysis of synchronous state machines. State minimization and introduction to state assignment. Each topic will have many examples which goes over them briefly with different parts. By end of chapter 2 and 4 there will be a quiz for you to test your understanding of that specific chapter.
Core subject of this course is digital design flow. Topics include PLDs, Flip Flops, latches, Digital Design flow, encoder, signals. By end of the course, you should be able to design, simulate, implement, and troubleshoot our VHDL codes using appropriate techniques and test bench.
This course is mostly for academic level Engineering students in different universities around the world.
Since you would be having a lifetime access to this course you would be able to revisit during your career as year passes to refresh your memory.
Instructor
The instructor of this course is Mehrad Nahouri. He has an Associates in Electrical Engineering concentration on digital field and is a lecturer at Rahsoft.
What is the target audience?
- This course is for students working in VHDL field.
- Undergraduate students
- Electrical Engineer
- Computer Engineer
- Graduate students taking VHDL course
- Researchers in VHDL field
Course content
- Introduction
- Basic Concepts of Digital
- Sequential vs combinational
- SR Latch
- Flip Flops
- PLD Family
- FPGA
- VHDL
- FIFO
- ISE Software
- Generic
- Synchronizing
- Test Bench
- ISE Simulation
- BCD code to Excess-3
- Demultiplexer
- Hierarchical and External Naming
Who this course is for:
- Electrical Engineers
- Computer Engineers
- Electrical Engineering Students
- Computer Engineering Students
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Basic Concepts of Digital -
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Basic Concepts of Digital
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Basic Concepts of Digital
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Sequential vs combinational
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Sequential vs combinational
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Sequential logic idea
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Sequential logic idea
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SR Latch
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SR Latch
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SR Latch
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SR Latch
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SR Latch
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SR Latch
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SR Latch
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SR Latch
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SR Latch
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SR Latch
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Timing Diagram
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SR Latch Timing Diagram
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SR Latch State Diagram
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SR Latch
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SR Latch with Enable
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D Latch
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D Latch Timing Diagram
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D Latch characteristic
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D Latch with transmission gate
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D Latch with transmission gate
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JK Latch
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JK Latch
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Flip Flops
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Flip Flops
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D Flip Flops
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D Flip Flops
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D Flip Flops
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D Flip Flops
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Latch vs Flip Flop
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Latch vs Flip Flop
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Latch vs Flip Flop
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Rising Edge D-FF
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Rising Edge D-FF
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Master Slave FF
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T Flip Flop
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Asynchronous Preset
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Synchronous Reset
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Additional Inputs of Flip Flop
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Setup time, Hold Time, Delay types
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Setup time, Hold Time, Delay types
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Timing Requirements
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Timing Requirements
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Timing Requirements
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Timing Requirements
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Synchronous vs Asynchronous
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Clock Signals
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Synchronous circuits
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Sequential circuit analysis
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Sequential circuit
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Sequential circuit
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Sequential circuit
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Sequential circuit
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Sequential circuit
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State table
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PLD Family
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Mask Programming Devices
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PLA
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GLA
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CPLD
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CPLD IC
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CPLD Architecture
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FPGA
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FPGA Architecture
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FPGA Architecture
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FPGA Architecture
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FPGA & CPLD Usage
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FPGA, SystemC, Verilog
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ISE Install
